13:29:42 the downside of having my primary monerod on a rockpro64 with only 4GB RAM - it's taking hours to scan the entire blockchain for blockchain-stats 13:39:09 2 hours to span 2014-2019 20:00:02 arguing with david Vorick about ASICs again https://twitter.com/hyc_symas/status/1476999837900021764 20:04:16 haters gunna hate 20:05:10 CNv2 ASICs worked on CN/R too (they were programmable): https://www.asicminervalue.com/miners/goldshell/st-box 20:05:21 they were much slower on CN/R though 20:06:01 did they outperform CPUs or GPUs? don't recall anyone really talking about them when CN/R came out 20:06:22 I want to see RandomX running on those ASIC chips, emulated floating point and all that good stuff 20:06:37 they did outperform CPUs and GPUs 20:06:42 14 kh/s @ 60 watts on CN/R 20:07:02 but they were no more than 10% of the total hashrate 20:07:22 lol ROI 1921 days 20:07:31 an eternity 20:08:31 quote from solar: "i'm willing to bet it was this hardware responsible for the cnv2 hashrate. it appears to be programmable, there are multiple areas in the code that appear to upload blobs over spi. it wouldn't make sense to manufacture a cn/r chip and add support for all the older variants anyway" 20:08:53 he promised to send me more detailed analysis back in November, but I haven't heard anything yet 20:10:05 programmable, wouldn't that necessarily be an FPGA then? 20:10:20 no, it was more like Cryptonight loop with several programmable hooks in it 20:10:31 ah 20:11:03 easy enough I suppose, to emulate the hooks in the C source 20:11:05 the idea was to make an ASIC that could handle all future Cryptonight tweaks 20:11:14 it worked well on CNv2, not so well on CN/R 20:11:58 it also explains why ASICs appeared so quickly on CNv2 20:12:15 they started the development right after CNv1 fork, maybe even before 20:13:32 yeah that would make more sense 20:14:32 so CN/R worked as intended in the end 20:18:58 hyc CPU cache latency is actually much worse than what ASIC could achieve. ASIC doesn't need all cache coherency protocols, cache tags and so on 20:19:14 it's 4-5 times difference in latency 20:19:48 in case with Cryptonight because ASIC only needs independent 2 MB chunks of SRAM 20:20:45 the rough approximation would be L2 vs L3 cache latency in CPU 20:21:31 CPUs can hide that latency fairly well with OoE (at least L1 and L2) 20:26:06 fair point 20:27:57 cache coherency is an issue for multicore chips sharing a cache. a single core CPU would also not have to deal with that 20:28:09 though I guess single core is a pretty rare thing these days