12:21:15 <sech1> hyc it might be finally time to look into RISC-V this year: https://www.youtube.com/watch?v=ykKnc86UtXg
12:22:14 <sech1> It's around $100 on Amazon, but delivery will take 3 months: https://www.amazon.com/VisionFive-RISC-V-StarFive-JH7110-Quad-core/dp/B0BGM6STN8/
12:22:56 <sech1> I'll probably try to setup QEMU VM first
12:52:28 <Inge> between pi3 and pi4 in perf
12:53:33 <sech1> Good enough to run Monero and P2Pool nodes
12:53:52 <sech1> And it lacks AES instructions too as far as I can see
12:55:52 <Inge> can risc-V support AES?
12:55:55 <Inge> i.e. hw
12:56:58 <sech1> https://riscv.org/blog/2021/09/risc-v-cryptography-extensions-task-group-announces-public-review-of-the-scalar-cryptography-extensions/
12:57:17 <sech1> RV64GC doesn't include this extension
12:57:25 <sech1> and that CPU is RV64GC
12:58:19 <sech1> It doesn't even have SIMD instructions and SIMD extension is not finalized yet, wow
12:59:06 <sech1> so if I start implementing JIT, it will be JIT without AES and SIMD at first
17:05:36 <hyc> maybe hold off a while longer then?
17:06:50 <sech1> RISC-V is not a single CPU, there will always be boards with or without AES or SIMD
17:06:57 <sech1> RISC-V JIT will need both variants
17:07:03 <sech1> btw AES is not a part of JIT
17:15:00 <hyc> sure, it's not part of randomx instruction set
17:15:06 <hyc> so only an issue for dataset init
17:22:57 <sech1> scratchpad init, and there is already software AES code available
18:30:54 <hyc> Sk Hynix showed off their processor-in-memory solution at CES 
18:31:00 <hyc> discussed here https://www.tomshardware.com/news/sk-hynix-to-showcase-gddr6-aim-memory-next-month
18:31:23 <hyc> typically these PIMs are quite limited, 32bit ALUs probably at most