16:35:43 <tevador> Btw, this whole thing is one FDIV_M RandomX instruction for RV64GC: https://paste.debian.net/hidden/93bdf103/
16:45:34 <sech1> Where did you get this code? RV64GC + vector instructions will be more compact
16:50:18 <tevador> I wrote it. We have to target RV64GC, which has no vector support.
16:50:36 <tevador> RV64GC is the "base" ISA for Linux.
16:53:43 <tevador> When I compile some code with GCC, it will use -march=rv64imafdc_zicsr_zifencei, so this is our base ISA, to be more precise. It has RV64GC + CSR + FENCE.I.
16:55:19 <tevador> It's safe to assume that anything that can run Linux will be at least rv64imafdc_zicsr_zifencei since that's what the linux kernel uses.
16:56:15 <sech1> X5 has vector instructions by the way
16:56:37 <hyc> then it must be C920, not C910
16:56:43 <tevador> Yes, I don't think you can get anywhere near x86 performance without the vector extension.
16:57:01 <sech1> are you using qemu, or did you get a real risc-v board?
16:57:34 <tevador> I have a board with SiFive U74
16:58:13 <sech1> nice
16:58:39 <sech1> qemu is too slow even on 7950X. But being able to run 32 threads kind of fixes it :D
16:59:03 <hyc> I'm still waiting for delivery of my lichee pi 4
17:00:33 <tevador> https://paste.debian.net/hidden/0faa7063/
17:01:39 <hyc> isa-ext seems rather unhelpful
17:04:23 <tevador> based on my research, the only reliable way to detect extensions is to run it and catch SIGILL...
17:06:52 <tevador> I'm really starting to appreciate the x86 cpuid instruction.
17:09:24 <sech1> Just assume RV64GC
17:09:35 <sech1> as minimum supported for RandomX
17:09:42 <sech1> and yes, test everything else
17:10:43 <sech1> As far as I can see, you only need to test vector instructions and aes instructions
17:10:53 <sech1> Everything else is covered by RV64GC
17:17:21 <sech1> I started working on ARM64 code for RandomX CFROUND abd AES tweaks
17:17:50 <sech1> Then I realized my RPi doesn't have AES, so I spent the day setting up aarch64 ubuntu in qemu
17:23:09 <tevador> RV64GC has no rotate and scaled addition, these need Zba and Zbb extensions.
17:23:30 <sech1> hmm, interesting
17:23:37 <sech1> no rotate, as in ROR/ROL?
17:23:42 <tevador> As for AES, I don't know any chips that support it.
17:24:04 <sech1> not a big deal, ROR/ROL can be replaced by a couple bitshifts + logical or
17:24:10 <tevador> Yes, rotate has to be emulated with shifts.
17:24:43 <tevador> 4 instructions instead of 1
17:25:09 <sech1> risc-v cryptography extensions are ratified already, so future chips will have aes
19:37:45 <tevador> Btw, there are at least 2 incompatible vector extensions being used in the wild: version 0.7.1 (SG2042 has it) and version 1.0.0. https://arxiv.org/abs/2304.10324
21:31:21 <hyc> sech1 you don't have an arm64 smartphone to run on?
21:36:39 <sech1> I have
21:39:04 <sech1> But I need to ssh into it somehow to use it as a "aarch64 dev machine", and I'm always too lazy to set it up. I only use it for final testing in termux
21:39:58 <sech1> btw I get 22 h/s in qemu on 7950X (single thread JIT)
21:40:20 <sech1> and overall it's fast enough to not be annoying :D
21:42:26 <hyc> heh
21:42:44 <hyc> I build it all on termux.
21:42:55 <hyc> doesn't take much to get the build env set up
21:43:13 <hyc> and you can install openssh in termux too
21:43:20 <hyc> ssh in is easy enough
21:44:07 <hyc> of course I usually clone the repos from my laptop. don't have the patience to download everything from the web again
21:45:39 <hyc> the other way I go, if it's just a quick compile/test, is leave the binary on my laptop, running tinyhttpd
21:45:50 <hyc> then just grab the binary on the phone using any browser
21:49:13 <sech1> plus, I can run 32 threads in randomx-benchmakr (dataset init is only 7 seconds)
21:49:16 <sech1> and 32 threads when compiling