17:24:51 hyc1 tevador oh boy, it looks like RandomX x86 JIT will need a big overhaul in the future: https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html 17:25:38 General purpose registers increased from 16 to 32, most instructions will have 3-operand variants (separate destination register), also move conditional instructions 17:26:06 *many new conditional instructions 17:47:25 lol that's no longer x86 :P 17:50:40 mips86 17:51:48 it's a welcome change. register renaming was always a shitty bandaid. 17:52:59 it might even make some compiler optimizations a lot simpler, matching other ISAs instead of all the bending-over-backwards compilers needed to do for x86 17:54:36 and it finally shuts up the nonsense of "it doesn't matter that we have few architectural registers because of register renaming and micro-op fusion etc etc etc" - it always mattered. 18:08:56 RandomX was designed to fit in 16 x86 registers though 18:09:15 I only found 1 place where the main loop saves data to stack 18:09:57 https://github.com/tevador/RandomX/blob/master/src/asm/program_loop_load.inc#L2 18:09:59 and line 12 18:10:10 it could use 2 temporary registers instead 18:10:18 but that's a minuscule save 18:11:05 And maybe 3-operand instructions will help to save a few cycles here and there 18:16:41 hmm, JIT could always use free registers to store values for IMUL_RCP instructions, just like in aarch64 JIT 18:20:44 3-operand encoding will help with IMUL instruction. Right now it requires MOV instructions to move the result to the intended register 18:21:18 *IMUL_H instruction