00:22:14 <hyc> So, the Thead C910 RISC-V processors have a major bug in their vector instruction set impl https://mastodon.social/@harold⊙mgp/112922089951656384
00:22:45 <hyc> one of the vector instructions accesses physical memory directly, with no virtual address translation
00:23:27 <hyc> some folks seem to be trying to make a big deal about it, but realistically there's about 0 software in the world that uses vector instructions on C910
00:24:08 <hyc> since that only implemented the version 0.7 draft of Risc-V vector spec, and only Thead's patched gcc generated code to use it
00:25:01 <hyc> there is absolutely zero code in kernel or system libraries using these instructions, so mitigation by disabling the vector extension will have zero impact on OS performance
07:49:26 <elucidator> https://www.securityweek.com/ghostwrite-vulnerability-facilitates-attacks-on-devices-with-risc-v-cpu/ Disabling the vector extension in the CPU mitigates attacks, but also impacts performance. => yeah but what kinda performance
07:55:08 <sech1> anything that does math
07:55:21 <sech1> or video encoding etc etc
07:57:22 <elucidator> Yeah I was addressing the article author because that's vague. Not everybody needs such work loads.
07:58:10 <elucidator> That kinda wording sounds like you disabled cache on a ryzen..
08:00:00 <\x> elucidator: its like disabling a cpu instruction
08:00:12 <\x> say disabling avx/2 on a modern cpu
08:00:24 <elucidator> Yeah, which wouldn't criple it as much 
08:00:34 <\x> well depends on software
08:00:38 <elucidator> Ofc
08:00:40 <\x> say you do A + BX
08:01:02 <\x> now you have to do it on two steps, B*X first then add A
08:01:09 <\x> not a straight up A + BX
08:01:21 <\x> some shit like that
08:01:44 <elucidator> Thanks for explaining basic vector math :)
15:34:56 <hyc> again, zero impact on the OS because nothing in the kernel or libraries would ever use those instructions
15:35:34 <hyc> maybe some impact in some specialized applications, because you had to go far out of your way to find a toolchain that supported that instruction set
15:44:08 <hyc> i.e., maybe some impact in code you built yourself, specifically for this obsolete instruction set...
15:44:33 <hyc> (like my abandoned effort to use the instructions in RandomX ...)
16:18:53 <sech1> hyc I tried to use AVX512VL (256-bit registers with) in RandomX, it didn't speed up anything. The idea was that a 256-bit wide register can hold 2 RandomX FP registers, and some instructions can be merged with some others: https://github.com/SChernykh/xmrig/tree/avx512
16:19:34 <sech1> like this: https://github.com/SChernykh/xmrig/commit/cd6eae15799d3bb9b30c1979c9787acbb04440e5