07:20:39 <sech1> XMRig finally got RISC-V support: https://github.com/xmrig/xmrig/pull/3724
07:21:01 <sech1> There were quite a few differences between the reference RandomX implementation and XMRig's code, so porting that was... not easy
07:21:23 <sech1> sorry, https://github.com/xmrig/xmrig/pull/3725
07:21:53 <sech1> XMRig 101 h/s vs RandomX becnhmark 87 h/s on a real board, this is interesting
07:22:06 <sech1> Given that the JIT compiler is essentially the same and both used large pages
10:51:07 <m-relay_> <g​ingeropolous:monero.social> nice!
12:21:19 <sech1> @hyc btw that board's CPU has 256-bit vector unit, and tevador's implementation doesn't use SIMD for RISC-V. I think it will be common for new RISC-V CPUs to have vector units 
12:23:00 <sech1> "Vector extension: RVV1.0 with VLEN 256/128-bit and x2 execution width"
12:23:49 <sech1> 512 KB L2 cache per core though, and no L3 cache
12:23:59 <sech1> but not bad for a $30 board