14:23:59 <sech1> Got a new toy to play with https://p2pool.io/u/8f4ac95d0af11879/20251120_152219.jpg 
14:24:24 <sech1> 8 RISC-V cores, 512 KB L2 cache per core, and it supports RISC-V vector extensions
14:25:02 <sech1> So my plan is to add vector extensions support to RandomX RISC-V code before Christmas
14:25:16 <sech1> But I don't have heatsinks for it yet, they'll arrive in a couple of weeks
14:45:14 <sech1> ahh, no... 512KB L2 cache is per a cluster of 4 cores, only
17:00:57 <hyc> heh have fun
17:01:10 <hyc> nice to have hardware with the official vector support now
18:18:12 <sech1> Unfotunately it has no AES support, and too small cache for RandomX. But it's a relatively cheap RISC-V board.