02:41:57 <eureka_> I don't think it's appropriate to say X9 was designed specifically for RandomX if it does end up being SG2044, the Sophon CPUs end up in many products 
02:42:49 <eureka_> that HPC benchmark comparison linked a few days ago was enlightening as to why the X5 didn't hit back-of-envelope potential hashrates, the memory controller is significantly less efficient than available on mainstream x86 chips
02:43:13 <eureka_> and with RandomX being very sensitive to memory performance, makes sense 
02:43:26 <eureka_> we won't find out what X9 is actually running for another several months :(
02:43:59 <eureka_> if change happens to be primarily memory controller improvements, that is a surprising performance leap 
02:44:10 <eureka_> less stalled cycles on the table
02:45:28 <eureka_> anyway, bitmain could probably make a CPU that natively implements the RandomX ISA but that would be far riskier than the RISC-V route (no pun intended :^)) and completely ignores any alternative markets 
02:46:04 <eureka_> sg2042 and sg2044 are rather appealing as general purpose CPUs, I would not mind having a server with one or two of them but the retail price is too much
02:47:36 <eureka_> chances of X5 or X9 having a high bandwidth interconnect from the CPUs to the controller is low, otherwise I would outright purchase one and work to achieve arbitrary code execution 
02:48:23 <eureka_> 1152 cores with only SPI/I2C or maybe a UART for outside connectivity is such a shame
02:58:40 <eureka_> @elongated; bitmain/sophon CPUs are still commodity/general purpose even though X5/X9 makes use of them. they're just in an unusual form factor compared to a typical server. there's no point in making RandomX less efficient for RISC-V as a whole