00:25:28 Add a kernel call (possibly two kernel calls - one for aesenc, one for aesdec) to that latency. It can't be efficient enough for the main loop AES. 01:36:21 I wonder if they do that AES for single rounds or do they have specific n round calls? 01:45:31 on the coprocessor 07:27:41 They must have N round calls, or even some sort of programming language for this accelerator 07:27:54 Something like OpenCL, but for crypto primitives 07:28:08 Someone needs to get their hands on SDK :) 07:31:22 https://github.com/sophgo/linux-riscv/tree/sg2044-dev-6.12 07:31:38 they have a couple of active branches here 07:33:39 https://github.com/sophgo/linux-riscv/tree/d74a073f36ecc302399bb0e5bf5b8b807400b798/drivers/soc/sophgo 07:42:09 forked from above too https://github.com/revyos/sg2044-vendor-kernel 07:42:51 https://github.com/revyos/sg2044-vendor-kernel/blob/35403068220226f17c364aaa45565e428a38c0c2/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi 07:43:07 this has isa extension list 07:46:03 /say // pka device, change size from 0x1000 to 0x6000 07:46:03 pka: pka@7040040000 { 07:46:03 compatible = "snps,designware-pka"; 07:46:59 actual list upstream on their repo https://github.com/sophgo/linux-riscv/blob/sg2044-dev-6.12/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi 07:47:04 that folder has more definitions 07:52:38 seems that just accelerates ECC/EdSA/RSA 07:54:52 it's probably another desingware IP if I had to guess 07:56:02 enjoy digging 08:06:25 I found all kinds of aes, even implementations for different architectures, but not their SPACC 08:09:36 #define SG2044_RST_SPACC 188 08:09:43 the only mention I found 08:27:55 indeed 20:02:47 well i got a benchmarking script working for windows in powershell, except for the msr mod. requires manual stuff. maybe we'll get more #s if windows users can bench 20:10:11 They can bench with xmrig (dev branch) 20:10:43 But it's hard to automate because xmrig doesn't auto-exit after benchmark finishes