14:49:54 @sech1 I just had a couple nits on the v2 PR. you can do something or just close them, then I'll approve 14:50:27 tests are fine here on amd64 and riscv64. need to dust off my arm64 linux box still 14:54:57 all good on my rk3399 14:58:25 Yes, I saw the notifications. I'll go through them today. Re 25 commits - they will he squashed of course 14:58:51 Before the final merge 20:47:45 sech1: Have you tested the v2 code with UBSan? 20:50:46 Hmmm. I have v2 code in p2pool already, and it runs an ubsan test. But not specifically v2. 20:51:27 I guess I need to compile with ubsan on arm64 and risc-v and test 21:30:36 ARM64 test: https://pastebin.com/DUuirQxu 21:30:49 I'll fix ARM64 code anyway because of possible alignment issues 21:31:18 But RISC-V code shouldn't have alignment issues, so I'll just test it for UB 21:31:31 But Debug build with UB sanitizer is sloooow, it'll take some time 21:40:56 Okay, risc-v test spitted a lot of "misaligned access" errors in unrelated places, I'll take a look 22:07:17 Yeah, misaligned access can just crash on some RISC-V machines. 22:09:05 I only see it complaining about 64-byte alignment because we have alignas(64) in virtual_machine.hpp 22:09:22 Technically it's just a performance optimization there, and can be ignored 22:15:03 RISC-V test: https://pastebin.com/PFrzAaPt 22:15:23 some bit shift UB, but it's not UB on RISC-V because RISC-V is defined as two's complement 22:15:37 and a lot of 64-byte alignment warnings, they can be ignored 22:17:22 ah no, found one: /root/RandomX/src/jit_compiler_rv64_vector.cpp:368:16: runtime error: store to misaligned address 0x7fffa75ff0ba for type 'uint32_t', which requires 4 byte alignment 22:17:50 one 4-byte and 370 64-byte alignment messages 22:35:31 Updated RISC-V test: https://pastebin.com/NfWM67EK 22:36:00 ah, I see it's already approved 22:36:19 hyc I'll wait a couple more days for you to review, and then push "squash-and-merge" button 22:59:26 The next step is monerod integration.