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tevador
sech1: which CFROUND tweak?
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sech1
calling it less frequently
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sech1
because right now it's 10% of loop time
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sech1
so if it's called 1/16th of a time (for example), it will boost hashrate by 10%
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sech1
on AMD CPUs
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sech1
we can use something like "some 4 bits of src register == mod.cond" to make it run 1/16th of a time
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tevador
we'd have to be careful with this not to underutilize the nonstandard rounding modes
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tevador
there are basically 2 options for this "ASIC" if it turns out to be real: 1. custom board with a bunch of ARM/RISC-V cores 2. VLIW core that implements the RandomX ISA in silicon
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tevador
2. should be possible to brick
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sech1
I don't think it will be possible to brick
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sech1
If they weren't stupid
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sech1
If they were, simple program size increase can brick it (it will not fit into internal buffers)
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sech1
Regarding CFROUND, it will still be executed 2048/16=128 times per program
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tevador
at best they could have implemented some kind of microcode to handle new instructions, which means we can't brick it, but we can make it slow
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sech1
There is a 1.4 GH/s miner on Hashvault now
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gingeropolous
pretty odd they are going after that 0.6 xmr block reward, but i guess ethereum mining is dead
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nioc
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m-relay
<gingeropolous:monero.social> i hope they actually sell this one. i wanna see what it is
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sech1
this miner looks more like another cloud server hacker
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hyc
why do we want to reduce CFROUND and "boost hashrate" just for the sake of boosting hashrate?
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hyc
hmm. 2023-08-18 17:36:43.294 W There were 94 blocks in the last 90 minutes,
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sech1
@hyc because it's 10% more RandomX IPC for all existing Ryzen and EPYC CPUs?
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sech1
less impact on Intel, but it's the point of RandomX - to be as close to real CPUs as possible
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sech1
so if some tweak gives better performance/watt on real CPUs and doesn't hurt ASIC resistance, it's a good tweak
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sech1
that solo miner dropped from 1.4 GH/s to 950 MH/s
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sech1
CFROUND tweak will make it 10% more efficient on Ryzens, 0-1% more efficient on Intel, and presumably will have the same ASIC resistance
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m-relay
<hbs:matrix.org> Has it been considered to have opcodes shuffled from one run to the other? Could that possibly affect a putative ASIC?
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tevador
the CFROUND tweak makes sense to implement; I also have some ideas for new instructions that could be added