the downside of having my primary monerod on a rockpro64 with only 4GB RAM - it's taking hours to scan the entire blockchain for blockchain-stats

2 hours to span 2014-2019

arguing with david Vorick about ASICs again twitter.com/hyc_symas/status/1476999837900021764

haters gunna hate

CNv2 ASICs worked on CN/R too (they were programmable): asicminervalue.com/miners/goldshell/st-box

they were much slower on CN/R though

did they outperform CPUs or GPUs? don't recall anyone really talking about them when CN/R came out

I want to see RandomX running on those ASIC chips, emulated floating point and all that good stuff

they did outperform CPUs and GPUs

14 kh/s @ 60 watts on CN/R

but they were no more than 10% of the total hashrate

lol ROI 1921 days

an eternity

quote from solar: "i'm willing to bet it was this hardware responsible for the cnv2 hashrate. it appears to be programmable, there are multiple areas in the code that appear to upload blobs over spi. it wouldn't make sense to manufacture a cn/r chip and add support for all the older variants anyway"

he promised to send me more detailed analysis back in November, but I haven't heard anything yet

programmable, wouldn't that necessarily be an FPGA then?

no, it was more like Cryptonight loop with several programmable hooks in it

ah

easy enough I suppose, to emulate the hooks in the C source

the idea was to make an ASIC that could handle all future Cryptonight tweaks

it worked well on CNv2, not so well on CN/R

it also explains why ASICs appeared so quickly on CNv2

they started the development right after CNv1 fork, maybe even before

yeah that would make more sense

so CN/R worked as intended in the end

hyc CPU cache latency is actually much worse than what ASIC could achieve. ASIC doesn't need all cache coherency protocols, cache tags and so on

it's 4-5 times difference in latency

in case with Cryptonight because ASIC only needs independent 2 MB chunks of SRAM

the rough approximation would be L2 vs L3 cache latency in CPU

CPUs can hide that latency fairly well with OoE (at least L1 and L2)

fair point

cache coherency is an issue for multicore chips sharing a cache. a single core CPU would also not have to deal with that

though I guess single core is a pretty rare thing these days