libera #monero-pow

9 Jan 2023

Monero's Proof of Work algorithm (RandomX) and related topics. Use #p2pool-log and #p2pool-mini for P2Pool discussions. Anti-spam active: PM hyc for voice.

• 12:21
  sech1
  hyc it might be finally time to look into RISC-V this year: youtube.com/watch?v=ykKnc86UtXg
• 12:22
  sech1
  It's around $100 on Amazon, but delivery will take 3 months: amazon.com/VisionFive-RISC-V-StarFive-JH7110-Quad-core/dp/B0BGM6STN8
• 12:22
  sech1
  I'll probably try to setup QEMU VM first
• 12:52
  Inge
  between pi3 and pi4 in perf
• 12:53
  sech1
  Good enough to run Monero and P2Pool nodes
• 12:53
  sech1
  And it lacks AES instructions too as far as I can see
• 12:55
  Inge
  can risc-V support AES?
• 12:55
  Inge
  i.e. hw
• 12:56
  sech1
  riscv.org/blog/2021/09/risc-v-crypt…-the-scalar-cryptography-extensions
• 12:57
  sech1
  RV64GC doesn't include this extension
• 12:57
  sech1
  and that CPU is RV64GC
• 12:58
  sech1
  It doesn't even have SIMD instructions and SIMD extension is not finalized yet, wow
• 12:59
  sech1
  so if I start implementing JIT, it will be JIT without AES and SIMD at first
• 17:05
  hyc
  maybe hold off a while longer then?
• 17:06
  sech1
  RISC-V is not a single CPU, there will always be boards with or without AES or SIMD
• 17:06
  sech1
  RISC-V JIT will need both variants
• 17:07
  sech1
  btw AES is not a part of JIT
• 17:15
  hyc
  sure, it's not part of randomx instruction set
• 17:15
  hyc
  so only an issue for dataset init
• 17:22
  sech1
  scratchpad init, and there is already software AES code available
• 18:30
  hyc
  Sk Hynix showed off their processor-in-memory solution at CES
• 18:31
  hyc
  discussed here tomshardware.com/news/sk-hynix-to-s…howcase-gddr6-aim-memory-next-month
• 18:31
  hyc
  typically these PIMs are quite limited, 32bit ALUs probably at most