"The first professional #XMR Miner, pioneering XMR Mining!" - nitter.net/BITMAINtech/status/1695783295806775605

> Support RISC-V, Available For Mining Multiple Cryptocurrencies

huh? cluster of RISC-V cores?

<interesting, since we never wrote a RISC-V JIT ourselves.

if it's real, it's yet another case of for-profit companies exploiting permissive licenses. free software deves should never use anything but GPL-family licenses

oddly the numbers look almost equal to tevador/RandomX #31 doing the math

212000 / 1350 ~= 157 vs 15000 / 95 ~= 157.9

that was an upper bound in efficiency at the time. and yet ryzens are alrady at the 150H/J region

212 kh? So I was right, it's those units that were mining since December 2021

which means this thing isn't any more efficient than current CPUs, so...

And power efficiency is not even impressive

those horizontal lines we've noticed after Christmas 2021 and in early 2022

ah right

so they're dumping 2 year old devices :D

2 years of "testing" :D

so they've been at it for at least 2 years, and all they could come up with is barely at parity with AMD

well, 2 years ago they were a bit ahead of best CPUs

now it's on par with tuned Zen4 CPUs

Zen4 EPYCs will be more efficient

yes, but to make an impact they needed to be more than 2x better. that was the threshold for GPUs to still be competitive on ETH

So nothing will change, they're already on the network

and mining

they're nowhere near that threshold

the ad says "multiple cryptocurrencies", so it's not even specialized. It's probably some custom RISC-V chips, but they're just regular CPUs

yep

but that's actually impressive for RISC-V to match AMD efficiency

they probably took some shortcuts

like 2 MB cache per core, but it's not shared between cores

which will save some energy and a ton of area

good point

yeah, plenty of easy optimizations if they don't need to run general workloads

I guess that "whoever designs a randomx chip will help in advancing cpus" is still true but I never expected for riscV :D

lol it kinda makes sense, no licensing restrictions

risc-v only because no need to pay fees

and it was the new hotness already

they didn't want to pay ARM fees :D

:)

all gud as long as they kinda contribute to riscV development iGuess

might be time for me to order a risc-v box from aliexpress

kico: wouldn't hold my breath on that

yeah sure

being optimistic here iGuess

but would be funny to see any bitmaintech names in LLVM/clang/gcc contributions

btw, back in early 2022 those "ASIC" workers we saw, they all had 250-300 kh/s reported hashrate on nanopool

I guess after 2 years of operation, they had to disable some of the units and reduce to 212 kh guarantee

overclocked and died :P

does this mean that "pow fork" is delayed for the time being?

this has no impact on pow decisions

The partial verification changes are useful for other reasons.

sure I mean no need for a "urgent fork" ?

yeah, the double hash to improve verification speed is worthwhile all on its own

I don't think there were any plans for an emergency PoW change

ok cool I got the wrong impression my bad :)

at this point tweaking the algo won't stop anyone, they're obviously using CPUs now so they can just update their firmware

I doubt tweaks will stop these devices, they're proper CPUs from the looks of things

yeah but we should not care about them anyway

the only things we could change that would make a substantial difference would be the on-chip cache requirements, and that would hurt all CPUs as well

moar L3, time to force multi threaded communication and atomics!

of course, we can target tweaks to kill these specific devices

like increase L3 until it exceeds what they have

sure but do we want to ?

No need

not like they're super efficient

Like I said, they've been mining for almost 2 years now

it would be fun to see their 2+ years of effort poof

and they don't have superior efficiency

but anything we did like that would only have a temporary effect

hyc, they already did ROI by now

it's better that we make tweaks that make regular CPUs more efficient

like my CFROUND tweak

it will make Zen4 more efficient than these ASICs

yeah I think we should care for regular users and not jihan

So far, RandomX works as it's been designed. If we do tweaks, we should focus on current and next generation CPUs.

agreed

<x​fedex:matrix.org> Ryzen 9 5950X (Zen 3, launch date 2020) is more power efficient than this ASIC.

I doubt they spent any effort on tuning the chips, and all their effort was on cramming a bunch of cores into a single case.

The only question now is the price

<x​fedex:matrix.org> I estimate that it would have to cost ~$3500 or less to be worth buying that ASIC over Ryzen CPUs

probably the best contriution they'd make to the world is in their physical build and cooling layout

They have ~2000 of those ASICs mining now

<k​4r4b3y:karapara.net> How did you get to that estimate?

judging by the hashrate of that ASIC miner (we know now it was Bitmain)

they have ~17% of the network

so around 400-450 MH/s

Not sure if they ever got their money back :D

all the more reason for them to start selling :P

<x​fedex:matrix.org> sech1: sorry, what is your CFROUND tweak?

it's a tweak that changes how often CFROUND instruction is triggered

it can boost Ryzen hashrate by up to 10% without changing anything else in RandomX

<x​fedex:matrix.org> is there any link for it?

so we had 10% "free" hashrate all this time

No link, but it was discussed in this channel before

<x​fedex:matrix.org> Found it: libera.monerologs.net/monero-pow/20230817

hmmm. I wonder - would it be more efficient to add pool support to monerod (so that its internal miner could work with p2pool) or

add hasher rpc to xmrig - so that it could do verification for both monerod and p2pool

so even after all the fuss in the original monero asic war, an asic company *still* decided to build and mine in secret

lol, of course.

that's what they do, why would they change

<x​fedex:matrix.org> hyc: the simplest thing to do which does not require any code change is running monerod with MONERO_RANDOMX_FULL_MEM and running p2pool with --no-randomx

and i doubt they even made these things capable of running anode, even though is a damn CPU

true milkers, not adding anything to the ecosystem

<x​fedex:matrix.org> gingeropolous: they OBVIOUSLY didn't

xfedex: yes of course. I wrote that code.

lulz, that nitter page; "guess the price". they are trying to find what the market will tolerate to buy their burnt out silicon

I use it 24/7 on my rockpro64. but I currently am not running xmrig on it because there wouldn't be enough RAM.

<x​fedex:matrix.org> I think the miner integrated in p2pool has performance similar to xmrig

<x​fedex:matrix.org> Does your device have enough RAM to run monerod without full memory and p2pool with RandomX fast mode?

probably. but that's still a couple hundred MB I'd prefer not to spend. anything that takes away from available FS cache hurts monerod perf

and memory limited devices, it's best to have full dataset in monerod and make everything else use calc_pow RPC call

*on memory

p2pool integrated miner has 5-10% lower performance even if you help it with manual MSR mod

because there are many code-level optimizations in xmrig

so... it might be worthwhile to add calc_pow RPC to xmrig itself, and point both monerod and p2pool at it

that's kind of backwards

why? let the fastest code do all of the hash computations

xmrig optimizations were always designed to make it faster, but never cared about being 100% correct all the time

ah

ok never mind

granted, it's correct now but I'm not sure I can give a guarantee :D

then back to the earlier idea, let monerod's miner work with p2pool

because I don't remember exactly, but at some point I considered optimizations that would make it 1% faster at a cost of 0.1% invalid hashes, for example

-f-unsafe-randomx-optimizations

well, just in case we want to brick this ASIC, I already found an instruction that's available on x86 and ARM (not all x86 and ARM, but many), but 100% is not there on that RISC-V chip.

on *that* risc-v chip?

do we know what they have, or custom design? given extensions are plenty

If they have risc-v chip, I know what they *don't* have :P

risc-v is an open standard, after all

and an instruction I picked, it's not even a finalized draft in risc-v, lol

*it's not ratified yet

and considering that they physically created their ASICs in 2021... It's 10000% not there

yeah, just saying that the standard includes instructions but there are many custom extensions on these risc-v chips out there

they probably have none though :D

They use RV64GC+Zk at best, which leaves a lot of unsupported instructions

RV64GC is a "standard" 64-bit RISC instruction set, Zk is needed for AES (I think)

yeah, unless they placed it in the non-standard extension in the "Guaranteed Non-Standard Encoding Space"

I bet they used as much standard stuff as possible to reduce costs

1350w? What is the claimed performance of the thing?

212 kh/s

about the same efficiency as Ryzen 5950X/7950X

I mean... I'm partial to RISC-V getting a leg up :D

On the other hand, adding an instruction that's not ratified in risc-v yet, will make trouble for all risc-v systems for the foreseeable future, not just for this ASIC. It's not ideal.

It will not make RandomX on RISC-V impossible, but it will make it noticeably slower

<p​olar9669:matrix.org> So are we now going to favour particular cpu architectures ? Because someone made cpus to mine monero

considering possibilities doesn't mean they will be pushed for at all

yeah, i mean, randomx is cpu-bound, and this RISC-V system is CPUs. I don't see the sense in modding the PoW to counter this development. I think time has already addressed the concern, and will continue to.