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m-relay
<polar9669:matrix.org> So only x5 would be affected ? Unless they have have a aes coprocessor
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sech1
I have no idea how it will be affected. The possible range of outcomes are from nothing changed to fully bricked
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sech1
What's more important is that consumer CPUs will be used more efficiently: 5-10% more RandomX instructions executed per second on each core, 2x more AES computations "for free"
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sech1
Most likely result for X5 will be 30% slowdown, if they implemented AES as a separate chip to initialize the scratchpad, and they don't have AES in their RISC-V CPUs
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m-relay
<polar9669:matrix.org> Consumer? You mean available to retail?
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gingeropolous
yep. that you can buy at your local bestbuy / costco / walmart
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m-relay
<polar9669:matrix.org> So only when rsic-v is available at a US retail store it would be considered non-asic-cpu?
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m-relay
<polar9669:matrix.org> So only when rsic-v is available at a US retail store it would be considered as consumer cpu ?
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m-relay
<polar9669:matrix.org> Btw rpi4 is available at Walmart
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moneromooo
You seem to be trying to twist things on purpose. This is called disingenuousness. It is regarded as a dishonest way to have a conversation. I suggest you try to avoid it.
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moneromooo
(Not only here, but several times before. One or twice is fine, but a pattern emerges)
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moneromooo
Being constructive is best, if you can.
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sech1
RISC-V is not an asic, and it's not a cpu. It's an open source instruction set and architecture
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sech1
When risc-v based cpus will be a noticeable part of Monero hashrate, then yes we'll be taking it into account in future tweaks (if any)
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sech1
And tweaks will be based on an architecture of actual cpus mining at the time
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sech1
Also, we still don't know X5 architecture. Maybe it has asic chips inside, and risc-v cpu is only used as controller/main cpu on the board
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m-relay
<polar9669:matrix.org> Anyway to know which cpus currently mine monero ?
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m-relay
<polar9669:matrix.org> Ok, will try avoid it
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hyc
can still order SiFive SBCs if you want to test and feel like writing a JIT
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hyc
we need some perf impact numbers on arm64 too for these new changes
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hyc
I'll try on my M1 macbookpro when I get a chance. can also try on my rk3399 rockpro64 later
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gingeropolous
my intels seem to be taking a slight hit
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gingeropolous
and i can't get huge pages on this one machine. blargh
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gingeropolous
hrm, huge pages problem hitting me on my A6-5200 as well. I use "sudo sysctl -w vm.nr_hugepages=1250" but it still says cache allocation fails
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sech1
your i7-6820HQ gets too low hashrates, you should double check it
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sech1
7700k only got 0.2% slower, we can ignore it
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sech1
It's expected, because they were already fast with CFROUND instruction, so they don't get this boost
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gingeropolous
ah yeah the 6820 boots with some stupid throttle. forgot about that
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hyc
are we sure this isn't actually penalizing Intel further? they were already inferior to AMD here
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tevador
0.2% is negligible, you have to consider that we're adding extra 262144 AES rounds and yet the hashrate barely changed
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sech1
If one part of Monero network (Intel) stays with the same hashrate, and another part (AMD) gets 5-10% more hashrate, then I count it as a win.
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sech1
For Monero network as a whole
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sech1
The important part is Intel CPUs still keep their hashrate, even when doing extra AES rounds
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sech1
btw latest Intel CPUs have faster AES than AMD (3 vs 4 clock cycles latency)
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m-relay
<charutocafe:matrix.org> does RandomX favor any specific ISAs?
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sech1
no, RandomX instruction set is a common denominator and it translates almost directly both to x86 and ARM
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m-relay
<charutocafe:matrix.org> do you know if anyone has tested RISC-V, PPC, or other ISAs?
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sech1
We don't have JIT compiler for these ISAs
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sech1
so it's not comparable
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tevador
btw, based on the 7700K benchmark, every hash needs 4584 extra cycles, so that's >57 AES rounds per cycle, not even an ASIC can do this
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sech1
at this scale (0.2%) it's hard to tell the real impact of changes, and count extra cycles
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sech1
it can swing the other way next time it's tested
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sech1
also, Intel CPUs should be tested with single thread
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sech1
because they all run 1 thread per core
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sech1
gingeropolous can you test your Intel CPUs with 1 thread?
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sech1
Use command line "--mine --jit --largePages --threads 1 --affinity 1 --init 16"
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sech1
Added my numbers for single thread Ryzen 7 1700, because it also runs 1 thread per core when mining
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sech1
It's even bigger speedup (more than 10%)
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selsta
I wanted to test on macOS ARM but seems the PR is not ready for that yet
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gingeropolous
magerd revert doesn't work. rm- r it is
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gingeropolous
still seeing that drop on single thread sech1
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sech1
Did you run each test several times? I found that it can jump +-5 h/s in both directions
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sech1
I run each test 5 times and choose the highest reported hashrate
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gingeropolous
i did just get Performance: 746.367 hashes per second on v2
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gingeropolous
and v1 Performance: 747.852 hashes per second
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gingeropolous
noice
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gingeropolous
wish i had the newest intel chips
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sech1
so -0.2%
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sech1
I could test it on Hetzner auction servers, but the newest they have is Core i7-8700
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sech1
and the first Intel CPUs with faster AES (3 cycle latency) are Ice Lake (only mobile) and Rocket Lake (11xxx desktop series)
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gingeropolous
so the 13700KF would do it?
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m-relay
<charutocafe:matrix.org> sech1: is a JIT compiler for other ISAs expected? especially RISC-V since its anticipated growth?
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sech1
Eventually (c)
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sech1
gingeropolous 13700KF would do it, yes