XMRig finally got RISC-V support: xmrig/xmrig #3724

There were quite a few differences between the reference RandomX implementation and XMRig's code, so porting that was... not easy

sorry, xmrig/xmrig #3725

XMRig 101 h/s vs RandomX becnhmark 87 h/s on a real board, this is interesting

Given that the JIT compiler is essentially the same and both used large pages

<g​ingeropolous:monero.social> nice!

@hyc btw that board's CPU has 256-bit vector unit, and tevador's implementation doesn't use SIMD for RISC-V. I think it will be common for new RISC-V CPUs to have vector units

"Vector extension: RVV1.0 with VLEN 256/128-bit and x2 execution width"

512 KB L2 cache per core though, and no L3 cache

but not bad for a $30 board