Implemented vectorized dataset init for RISC-V: before p2pool.io/u/ceef12e3b3b4e8ea/Screen…%20from%202025-11-30%2015-57-46.png after p2pool.io/u/3ef318b4f6ea6660/Screen…%20from%202025-11-30%2016-00-21.png

dataset init time reduced from 28.294 s to 21.728 s

30% speedup, but it also includes the cache init part which didn't change

cache init is 5-6 seconds, approximately

so dataset init time reduced from ~22 to ~15 seconds

In theory it would be down from 22 to 11 seconds if RAM access wasn't a bottleneck

Got even faster after fixing all the bugs: p2pool.io/u/8c593a881a361d8b/Screen…%20from%202025-11-30%2018-58-54.png

from 28.294 down to 17.018 seconds to init dataset

👏

Next on my plan is to write vectorized soft AES for hash/fill AES to speed up this part. After that I'll be comfortable enough with RISC-V assembly and vector instructions to add it to the actual RandomX JIT

(Because this CPU doesn't have hardware AES, sad)

`RxDataset::init` timings: 21865 ms before, 10639 ms after

That's more than 2x speedup, lol

I expected max 2x from vector code

they might have way more vector registers than scalar ones nowadays :D

I guess vector instructions are overall more efficient

Or it's the fact that I do prefetch instructions in vector code, and scalar code doesn't

It's the same number of registers (32)

physical vs virtual I mean

ah, maybe it's also that register width is 256 bit (4x scalar)

but execution units are 128 bit

oh, double pump!

so it is 2x faster, but executes 4x fewer instructions, and some additional speedup comes from this

so it saves time on instruction decoding

I'm so sad Intel fucked up AVX512 so bad on new cpus

E cores didn't have 512 so they dropped it entirely

AMD: here's double-pumped AVX512, next gen, full pump

yes, it's 512 physical in Zen 5

Intel is trying to define AVX10 to take into account bitwidth

though they could have just double pumped it :')

I had an idea to write AVX512 dataset init, but it makes little sense. It's already less than a second on 9950X with AVX256

all the useful stuff in AVX512 that is not explicitly 512-bitwidth is so great

and what was that OP that was slower than implementing it yourself, not just yourself with vector instructions but with scalar :D

made people not use that at all due to slowdown

AMD: 1 cycle execution time

no one uses it, so just about a flex