looks like 256-bit vector width is kind of a standard for RISC-V CPUs with vector support: cdn.mos.cms.futurecdn.net/waPNfjysh8LBEhHraZZiTh.png

So I'll target 256-bit width in all my RandomX code

Btw that CPU is designed by Jim Keller (AMD Zen, Apple M series)

wow, even monsters like this exist: p2pool.io/u/37d40fdffe1ab072/image.png

512 bit wide vector unit

and 4 MB L3 cache per core

will be a monster for RandomX

fun stuff

sech1: Which RISC-V board are you using? Orange Pi?

jpk68: 15:23:59 <@sech1> Got a new toy to play with p2pool.io/u/8f4ac95d0af11879/20251120_152219.jpg

Orange Pi RV2

Thanks. Missed that photo somehow

Unfortunately it seems pretty hard to find RISC-V boards with reliable hardware AES. IIRC the performance gain from the Raspberry Pi 4 to 5 (which added hardware AES) was fairly substantial.

I'm working on writing vectorized software AES for RISC-V, it should be much faster than the regular code.

Oh, cool

Is AES used for anything other than filling/hashing the dataset and scratchpad? I'm not too knowledgeable about what takes the most time per hash

I know this is a terrible comparison, but the Pi 5 is around 5x faster than my RISC-V board, which also has 4 cores.

fAES is used in multiple parts of the algorithm

soft aes is around 30% of RandomX hash time

so if I make it 2x faster, hashrate will increase by ~15%