Inge, at this point i don't think its about hamstringing Rx on the x5. Its about improving rX and it happens to hamstring x5. the fact that new gen amd chips have less hash ( or whatever was stated) means that somethings borkt

We have antpool now: miningpoolstats.stream/monero

19.8 MH/s

<r​ecanman:agoradesk.com> Quick question, how do these websites determine which hashrate is coming from which pool?

<k​arano:poddery.com> Ip ?

They just show whatever pools say

Of course there are a few checks in place

<r​ecanman:agoradesk.com> Ah, right. I didn't think of that, thanks

<r​ecanman:agoradesk.com> 🤦‍♂️

<k​arano:poddery.com> If they want to hide their hashrate , i guess they could simply use another ip for it , which is not regsitered with this website

Then it would be shown in the "unknown blocks" anyway

Right now unknown is 2.5%

<k​arano:poddery.com> Yeah

gingeropolous: thanks for clarifying

hmm, so the X5 is "multicoin" - yet their own pool list only contains XMR for RandomX

i guess by multiple coins they mean the xmr you mine today and xmr you mine tomorrow :D you get two "coins" of the same currency :P

beside the joke, i think we can expect a firmware upgrade shortly to address other randomX coins problem

qu.ax/lcLH.png roi in 1 year if you got that initial discount ?

well ROI in one year, if you don't spend 4x as much replaced overheated burnt out boards in it :P

they still only list the initial firmware, no "tf card service pack" still wondering where the hell is rV binaries

it's possible that the controller board cross compiles the risc-v code for the mining boards, did we see any indication for this?

I'm reasonably sure it can mine Townforge gold, since it's merge mined with monero. That'd make it multi-coin. Technically.

I tried to register and mine at antpool, but without success

When I switch to XMR page to get pool URL, it just logs me out :D

But it does show pool URLs for a split second before that. I tried these pool URLs but I only get "connection reset by peer"

xmr.antpool.com:3333, xmr.antpool.com:443, xmr.antpool.com:25

"connection reset by GFW"

Maybe they use some proprietary protocol that only works with X5

In this case, antpool hashrate is 100% from X5 miners

Found one more URL xmr.antpool.com:9005

This one is working with xmrig

i think the magic is inside the arm64 kernel image, it has some stuff i can't get a hold of. some LZO compressed data and xz compressed data that i'm speculating related to rV part

But can you decompress it?

nope

both says "corrupted"

for the lzo i checked in hex editor to see if i got the blob with right size, checked the headers, all seems correct, "it just can't extract TM"

well, the decompression code should be there somewhere

yeap, still checking bits and pieces i might have missed before deep diving those

like the stuff in godminer binary, they don't ever clean up their codebase i think, this has stuff related to all the previous coins like LTC, RVN, ZEC etc.

very weird stuff comes up, when checking strings, there's an ascii hex string, that turns out to be raw inflated data but doesn't result anything interesting

i wouldn't be surprised to learn it's a firmware for a mcu on board, i see references of dspic33 series

and some funny strings like "Pool is activing, exiting and restart."

This is "all your base are belong to us" level :D

hmm Antpool is around 20Mh/s so they have around 100 devices online? Since we know the estimated hashrate of each one, we can quickly see how many are active :D

Yes

Normal XMRig can technically mine there (I checked it), but I don't think anyone but X5 owners will mine there

so 100 X5s still haven't burned down?

I think 100 X5s found their way to customers

Bitmain uses nanopool, supportxmr and hashvault for mining

hmm and they all landed at the exact same time since Antpool went from like 100kh/s to 20mh/s instantly

or is this the X6 getting tested out?

I don't think so

X5 is state-of-the-art RISC-V, nothing to improve for X6 apart from cooling and firmware

Maybe they moved 100 devices to antpool to ensure it mines enough blocks per day

hmm could be the case, increases the popularity of the pool by moving it up the listings and advertises their products

I still wonder what "R" stands for in SG2042R

Reject?

So chips that didn't have all 64 cores working?

especially since all of the youtubers have slated the X5

and they decided to repurpose them :D

would they screen print Rejected on their hardware on purpose? :P

Maybe "Reduced"

to 32 cores

It makes sense that they would use quality rejects for X5

Since they can't sell them normally

Normal CPU company would just make another CPU model, like SG2040 with 32 cores :D

Like AMD does with their 8-core chiplets - reduces them to 6 cores for low-end models

Ryzen 7950X -> 7900X

Youtubers didn't like X5 because it can only mine Monero.

Zephyr is all the hype now

So they were disappointed

doesn't look good when the "celebs" hate on your "shiny" "new" product :D

its also never good when you take so much time and effort over your marketing strategy for a release, and then you send out something that doesn't live up to anywhere near its expectations

might see some on the marketplaces soon for a nicely reduced price

Hashrate and power usage is as promised though

btw DDR4-3200 8GB SODIMM sticks can be found for as low as $25

they "Supermicor server certified" sticks for $100 each

*they use

At least they didn't cheap out there :D

wonder if the manufacture dates of the memory are all the same, or if they just bulk bought retail :D

<@sech1> I still wonder what "R" stands for in SG2042R => stands for "ROI in 20 years at best"

<c​trej:matrix.org> lol

the .bmu firmware results in a 32bit arm userland "distro". in it there are those update_app and update_total files. and update_total has 64bit arm tools. so there's one main arm that has the cgminer, godminer, webui stuff, then there's the controller one with smaller firmware. what if the R has the controller ARM embedded ? i wonder if they have a "loicence" for that. arm+riscV cores on the same package.

it seems they are using xxtea for encrypting eeprom data/config. there's even what seems to be a default key but i think that ram location is already getting updated for the real key.

yeah, hardware_init function is calling those two xxtea functions to decode and encode. maybe there's a default blob we are missing that's encrypted with this.

Ohh, juicy: techpowerup.com/314231/amd-zen-5-mi…tecture-referenced-in-leaked-slides

10-15% IPC increase over Zen 4

I did a quick compare with Zen 4:

dispatch/rename: 6 -> 8 wide, +33%

ALUs: 4 -> 6, +50%

load/stora: 3/2 -> 4/2, +33%

L1 data: 32 -> 48 KiB, +50%

L2/L3: same

Zen 5 will be more efficient than X5, for sure :D

hyc1 techpowerup.com/314231/amd-zen-5-mi…tecture-referenced-in-leaked-slides

33% wider dispatch, 50% more ALUs, 50% bigger L1

Zen 5 can execute 8 ops/cycle, wow

sounds cool. of course real throughput will never get near that

They expect 10-15% IPC increase

8 ops/cycle is 2 times more than Zen 1 :D

They're getting to the point where 2 threads per core is not enough :D

IBM have been running what, 8 threads/core?