hyc1 tevador oh boy, it looks like RandomX x86 JIT will need a big overhaul in the future: intel.com/content/www/us/en/develop…ced-performance-extensions-apx.html

General purpose registers increased from 16 to 32, most instructions will have 3-operand variants (separate destination register), also move conditional instructions

*many new conditional instructions

lol that's no longer x86 :P

mips86

it's a welcome change. register renaming was always a shitty bandaid.

it might even make some compiler optimizations a lot simpler, matching other ISAs instead of all the bending-over-backwards compilers needed to do for x86

and it finally shuts up the nonsense of "it doesn't matter that we have few architectural registers because of register renaming and micro-op fusion etc etc etc" - it always mattered.

RandomX was designed to fit in 16 x86 registers though

I only found 1 place where the main loop saves data to stack

and line 12

it could use 2 temporary registers instead

but that's a minuscule save

And maybe 3-operand instructions will help to save a few cycles here and there

hmm, JIT could always use free registers to store values for IMUL_RCP instructions, just like in aarch64 JIT

3-operand encoding will help with IMUL instruction. Right now it requires MOV instructions to move the result to the intended register

*IMUL_H instruction