@sech1 I just had a couple nits on the v2 PR. you can do something or just close them, then I'll approve

tests are fine here on amd64 and riscv64. need to dust off my arm64 linux box still

all good on my rk3399

Yes, I saw the notifications. I'll go through them today. Re 25 commits - they will he squashed of course

Before the final merge

sech1: Have you tested the v2 code with UBSan?

Hmmm. I have v2 code in p2pool already, and it runs an ubsan test. But not specifically v2.

I guess I need to compile with ubsan on arm64 and risc-v and test

ARM64 test: pastebin.com/DUuirQxu

I'll fix ARM64 code anyway because of possible alignment issues

But RISC-V code shouldn't have alignment issues, so I'll just test it for UB

But Debug build with UB sanitizer is sloooow, it'll take some time

Okay, risc-v test spitted a lot of "misaligned access" errors in unrelated places, I'll take a look

Yeah, misaligned access can just crash on some RISC-V machines.

I only see it complaining about 64-byte alignment because we have alignas(64) in virtual_machine.hpp

Technically it's just a performance optimization there, and can be ignored

RISC-V test: pastebin.com/PFrzAaPt

some bit shift UB, but it's not UB on RISC-V because RISC-V is defined as two's complement

and a lot of 64-byte alignment warnings, they can be ignored

ah no, found one: /root/RandomX/src/jit_compiler_rv64_vector.cpp:368:16: runtime error: store to misaligned address 0x7fffa75ff0ba for type 'uint32_t', which requires 4 byte alignment

one 4-byte and 370 64-byte alignment messages

Updated RISC-V test: pastebin.com/NfWM67EK

ah, I see it's already approved

hyc I'll wait a couple more days for you to review, and then push "squash-and-merge" button

The next step is monerod integration.